1. Field of the Invention
The invention relates to a processor and an instruction control method for executing instructions by dynamic pipeline scheduling. More particularly, the invention relates to a processor and an instruction control method for controlling issue of instructions to different kinds of arithmetic operating units.
2. Description of the Related Arts
Hitherto, in a processor for executing dynamic pipeline scheduling, processes are executed separately by three units: an instruction issuing unit of in-order depending on program order; an instruction executing unit of out-of-order which does not depend on the program order; and a committing unit of the in-order depending on the program order. That is, the instruction issuing unit fetches instructions by the in-order, decodes them, and allows a reservation station to hold the instruction operation (OP code or the like) and an operand. As soon as all operands are prepared in the reservation station and an arithmetic operating unit is made usable, the instruction executing unit speculatively executes the instruction by the out-of-order and obtains a result. The committing unit discriminates a commitment of the instruction on the basis of a branch prediction result or the like, completes the instruction by the in-order, and stores the execution result into a register file or a memory (only in the case of storage). In the processor using such dynamic pipeline scheduling, a plurality of different kinds of arithmetic operating units are provided for the instruction executing unit and it is necessary to control so as to issue an instruction in accordance with the kind of arithmetic operating unit.
FIG. 1 is an explanatory diagram of instruction issue control in the conventional processor. For example, four instruction word registers 100-1 to 100-4 are provided for an instruction issuing unit. Four instructions are simultaneously fetched from an instruction cache and decoded. The instructions in the instruction word registers 100-1 to 100-4 are issued to reservation stations 108-1 and 108-2 via a selecting circuit 102 and a priority switching circuit 106. For example, a multiplication/division arithmetic operating unit 110 and an addition/subtraction arithmetic operating unit 112 are provided for the instruction issuing unit. The multiplication/division arithmetic operating unit 110 can also execute an adding instruction and a subtracting instruction in addition to a multiplying instruction and a dividing instruction. The addition/subtraction arithmetic operating unit 112 can execute the adding instruction and the subtracting instruction but cannot execute the multiplying instruction and the dividing instruction. Therefore, the multiplying instruction, the dividing instruction, the adding instruction, and the subtracting instruction are issued to the reservation station 108-1 provided in correspondence to the multiplication/division arithmetic operating unit 110. The adding instruction and the subtracting instruction are issued to the reservation station 108-2 provided in correspondence to the addition/subtraction arithmetic operating unit 112. Since the adding instruction and the subtracting instruction can be executed by both of the multiplication/division arithmetic operating unit 110 and the addition/subtraction arithmetic operating unit 112 arranged symmetrically when they are seen from the instruction word registers 100-1 to 100-4, they are defined as symmetry instructions. On the other hand, since the multiplying instruction and the dividing instruction can be executed only by the multiplication/division arithmetic operating unit 110 locating asymmetrically when it is seen from the instruction word registers 100-1 to 100-4, they are defined as asymmetry instructions. The selecting circuit 102 sets an issuing destination at the time when the symmetry instructions are fetched into all of the instruction word registers 100-1 to 100-4 and decoded. In the example, the selecting circuit 102 sets the reservation station 108-1 as an issuing destination of the instruction word registers 100-1 and 100-3 and sets the reservation station 108-2 as an issuing destination of the instruction word registers 100-2 and 100-4. When the asymmetry instructions are fetched into one of the instruction word registers 100-1 to 100-4 and decoded, the priority switching circuit 106 switches the issuing destination so that the issuing destination of the instruction word registers holding the asymmetry instructions is set to the reservation station 108-1. Thus, the asymmetry instructions in which a frequency of generation is low are certainly issued to the reservation station provided in correspondence to the multiplication/division arithmetic operating unit 110.
FIGS. 2A and 2B show a case where an adding instruction Add has been fetched as a symmetry instruction into all of the instruction word registers 100-1 to 100-4 and decoded with respect to the prior art of FIG. 1. First, in FIG. 2A, the adding instruction Add is issued to the reservation stations 108-1 and 108-2 as issuing destinations set by the selecting circuit 102 from the instruction word registers 100-1 and 100-2. Subsequently, as shown in FIG. 2B, the adding instruction Add is issued to the reservation stations 108-1 and 108-2 as issuing destinations set by the selecting circuit 102 from the instruction word registers 100-3 and 100-4. FIGS. 2A and 2B show processes of the same decoding cycle.
FIGS. 3A and 3B show a case where a multiplying instruction Multiply as an asymmetry instruction has been fetched into the instruction word register 100-1 and decoded and the adding instruction Add has been fetched as a symmetry instruction into the residual instruction word registers 100-2 to 100-4 and decoded with respect to the prior art of FIG. 1. First, in FIG. 3A, the multiplying instruction Multiply is issued to the reservation station 108-1 as an issuing destination set by the selecting circuit 102 from the instruction word register 100-1. At the same time, the adding instruction Add is issued to the reservation station 108-2 as an issuing destination set by the selecting circuit 102 from the instruction word register 100-2. Subsequently, the same processes as those in FIG. 2B are executed in FIG. 3B.
FIGS. 4A and 4B show a case where the multiplying instruction Multiply as an asymmetry instruction has been fetched into the instruction word register 100-2 and decoded and the adding instruction Add has been fetched as a symmetry instruction into the residual instruction word registers 100-1, 100-3, and 100-4 and decoded. First, in FIG. 4A, although the issuing destination of the instruction word register 100-2 is the reservation station 108-2 set by the selecting circuit 102, since this setting is incorrect, the priority switching circuit 106 in FIG. 1 operates so as to switch the issuing destination of the instruction word register 100-2 to the reservation station 108-1. Thereafter, the multiplying instruction Multiply is issued. Subsequently, the same processes as those in FIG. 2B are executed in FIG. 4B.
FIGS. 5A and 5B show a case where the multiplying instruction Multiply as an asymmetry instruction has been fetched into the instruction word register 100-3 and decoded and the adding instruction Add has been fetched as a symmetry instruction into the residual instruction word registers 100-1, 100-2, and 100-4 and decoded. In this case, the instructions are issued in accordance with the setting of the selecting circuit 102.
FIGS. 6A and 6B show a case where the multiplying instruction Multiply as an asymmetry instruction has been fetched into the instruction word register 100-4 and decoded and the adding instruction Add has been fetched as a symmetry instruction into the residual instruction word registers 100-1 to 100-3 and decoded. First, FIG. 6A is the same as FIG. 2A. Subsequently, as shown in FIG. 6B, although the issuing destination of the instruction word register 100-4 is the reservation station 108-2 set by the selecting circuit 102, since this setting is incorrect, the priority switching circuit 106 in FIG. 1 operates so as to switch the issuing destination of the instruction word register 100-4 to the reservation station 108-1. Thereafter, the multiplying instruction Multiply is issued.
In such conventional instruction issue control, however, in the case of FIGS. 4A or 6B, since the instruction issuing destination set by the selecting circuit 102 is incorrect, it is necessary to control so as to discriminate such an incorrect situation and switch the issuing destination by the priority switching circuit 106. Thus, a control logic in the decoding cycle becomes deep by an amount corresponding to the control for switching the issuing destination by the priority switching circuit 106. That is, there is a problem such that the improvement of an operating frequency of the processor is made difficult due to the addition of the priority switching circuit in the decoding cycle.